If a company is the largest semiconductor manufacturer in the world, it needs to set forward-looking corporate goals in order to maintain its position in the industry and stay ahead of its competitors. Intel Corp set the 10nm process technology as the company's forward-looking goal, but due to the great delay of the 10nm node technology, Intel Corp had to change the company's technological blueprint (Road Map).

Intel Corp even fell into the dilemma of having to discuss the adoption of other strategies. today, although Intel Corp is still researching and developing for the 10-nanometer process, because TSMC and Samsung Electronics are committed to 7-nm, 6-nm, 5-nm and higher-level processes, where is Intel Corp's current gap?

Intel Corp, who is in trouble

To develop a new process technology, enterprises need to set certain goals for performance, power, area (PPA:Performance, Power, and Area). Under the "Tick-Tock mode (tick-tock mode, process year-architecture year)" of Intel Corp's processor and Microarchitecture, all the content of PPA has been improved and developed.

Intel Corp's goal is to increase the density of 10nm (also known as "Intel 1274") transistors to 2.7times that of 14nm and improve performance by 25 per cent.

Judging from the recently announced 10nm characteristics, very similar to the first generation of TSMC's 7nm process (N7), Intel Corp had planned to start the 10nm process in 2016 (about two years earlier than TSMC's N7 mass production time). If it goes according to plan, Intel Corp will far outperform his competitors in HPC (High Performance Computing).

Intel Corp called "increasing the density of the transistor"Hyper Scaling". Later, because the yield was lower than expected and the cost was higher than 14 nanometers, Intel Corp had to re-examine the goal. On the other hand, as far as 10nm process is concerned, in order to maintain Moore's Law, maintain the smaller size of wafers (Die Size), and cut costs, 10nm process requires more miniaturization technology than other processes.

In Intel Corp's 10nm process, FinFET transistors and 13-layer metal stacks (Metal Stack) are used. As a mainstream technology to promote the implementation of "Hyper Scaling", first of all, COAG (Contact Over Active Gate) is needed.

Due to the use of Co (cobalt, Cobalt) Inter Connect (cobalt interconnect) technology in the initial two layers, the resistance per unit area is reduced by 50% compared with W (tungsten, Tungsten). In addition, in order to reduce the above interconnects (Inter Connect), electron migration is reduced from 5max 1 to 10max 1.

In addition, in the former process (FEOL, Front End of Line) to make Fin, there are SAQP (Self-Aligned Quadruple Patterning, self-aligned quadruple pattern) and SADP (Self-Aligned Double Patterning, self-aligned double pattern) methods, and the back process (BEOL, Back End of Line) can also be used as a SAQP method for making special metal layers. In addition, there are technologies such as Single Dummy Gate, and the most popular method is listed above.

Since all the existing cutting-edge process technologies rely on multiple patterns (Multi-patterning), to achieve the specific functions of Intel Corp's 10nm process, 4xMagne 5xmem6x patterns (Patterning) are required.

However, in order to achieve a certain function, the wafer needs to be exposed six times, which is the most complicated. As far as multi-pattern (Multi-patterning) is concerned, the production cycle is long and there are many defects, so the product yield is low, the cost is high and the income is low. It can be said that in order to obtain "Hyper Scaling", it is a very risky choice to use too many patterns (Multi-patterning) without using EUV (extreme Ultraviolet Lithography).

In addition, Intel Corp is the only semiconductor manufacturer that uses SAQP for 7nm and 10nm BEOL, so there is a view that "SAQP leads to high defect density".

There are many reasons for using Co and Ru (Ruthenium, ruthenium) in the 10nm (and higher intergenerational) process. However, when Intel Corp was committed to the research and development of 10nm, Co was a relatively new material, so there is also a view that "the reason for the high density of product defects is Co". The latter view is obviously not "blaming others", because the adoption of Co requires the use of a new inspection tool (using an electron beam).

Compared with the current optical inspection tools, the speed of the single beam (Single Beam) inspection tool is slow (the Multi electron beam tool is still in the stage of development and is also very slow). However, as far as optical inspection tools are concerned, the new (or under development) process is not clear enough. Therefore, at present, the electron beam tool can only be used for process quality verification, correction (Calibration) and other purposes.

It is not uncommon for Intel Corp to take risks and adopt new technologies ahead of other manufacturers in the industry. However, as far as the research and development of 10 nm is concerned, it has gone far beyond the framework of "reform" and the risk is extremely high.

Nathan Brookwood, an investigator with Insight 64, a US market research company, said: "according to relevant people in the industry, looking back at history and looking at the whole Intel Corp, there is no doubt that Intel Corp is full of aggressive attacks."

Delayed start-up of 10 nm

Intel Corp first announced the 10-nanometer process in July 2015. At that time, Intel Corp pointed out that this process has the problems of high defect density and low yield of Multi-patterning. Moreover, the mass production of 10nm (product name: Cannon Lake) is in the second half of 2017, about a year later than originally planned.

"Cannon Lake has started small-scale mass production and plans to start mass production in the second half of 2018," Intel Corp said at the beginning of 2018. However, in April 2018, Intel Corp announced: "due to the low yield, the mass production of 10-nanometer process CPU has been postponed to 2019." Later, the second generation of 10nm process was mass-produced in 2019 (be careful not to be confused with the 10nm + process), which has obvious advantages over the first generation of 10nm technology in many aspects.

Intel Corp himself should have known the pros and cons of the 10-nanometer process in 2015 (the time of the first official announcement) or even before. On the basis of fully understanding the risks, Intel Corp realized that it is necessary to mass produce CPU that matches cost, performance and market investment time in the next few years.

Therefore, at the beginning of 2016, Intel Corp released a new basic concept with the aim of introducing new process technology and micro-architecture (Microarchitecture). In other words, the decade-long "Tick-Tock model (tick-tock model, process year-architecture year)" came to an end, and the new "PAO (process-Architecture-Optimization)" began to appear. That is, through long-term optimization of micro-architecture (Microarchitecture), repeatedly improve the process technology, product design.

Brookwood pointed out that the "Tick-Tock model" is one of the risk reduction strategies, using the existing micro-architecture (Microarchitecture), making trial and error on the new process (Debug), and then introducing the new micro-architecture into the validated process, thus achieving annual performance improvement.

A former employee of Intel Corp once made it clear that from the market's point of view, "Tick-Tock" itself is a model born to obtain high evaluation, and when management examines this model, it also promotes the realization of this model regularly and regularly. Therefore, there is no doubt that everyone is working towards the goal, and everyone has forgotten how difficult this model really is.

Brookwood said that over the past decade, "Tick-Tock" has played its full role. However, there was a slight "fall" in 14nm, resulting in an one-year delay in mass production and a complete "collapse" in the 10nm process!

On the other hand, TSMC maintains a biennial update pace, although the performance improvement of TSMC is not very fast, but the accuracy of performance prediction is very high. No one would have thought that when Intel Corp was still "hovering" at 14nm, AMD had entrusted almost all series of products to TSMC's 7nm process.

"14nm +" is an optimized version of Intel Corp's 14nm process. Compared with the "Skylake" with the 14 nm process, the power consumption of the "Kaby Lake" with the "14 nm +" process is only 15% higher, with little improvement.

In addition, the further optimized version of "14 nm + +" has a gate distance (Gate Pitch) of 84 nm (an improvement compared with 70 nm under the 14 nm process) and a 24% increase in driving current, resulting in a reduction in power consumption of about 50%.

Intel Corp's "14nm + +" is mainly used in processors named "Coffee Lake" and "Comet Lake" (mainly used in high-end desktop game console PC, high-end PC and other products). As Intel Corp will continue to devote himself to the research and development of processors in the future, there will be not only 10nm chips 10nm plus, there should also be 7nmmiles 7nmcycles 7nmchips +.

On the other hand, Intel Corp's CEO also seems to be considering "extending the benchmark time for research and development of major technologies from two years to two and a half years". But what result can this bring to Intel Corp? Without the test of time, there is no way to know.

The head of Intel Corp's enterprise information management department has said that our goal is to update the technology every year to support the company's product blueprint (Road Map). Therefore, the effect of improving PPA can be achieved by miniaturizing the process node (Process Node) and improving the internode (Internode) at the same time.

What Intel Corp has to change is not just the R & D method of the production process.

A long time ago, due to the adjustment of product design and production technology, Intel Corp had to use a special process when carrying out a certain product design. However, the research and development of products and process technologies have been separated, so that the most feasible technologies can be applied to the research and development of CPU and GPU planned for future releases.

This model is similar to the relationship between Fabless Chip Maker (chip designer) and Foundry. GLOBALFOUNDRIES's former CTO (Chief Technology Officer, CTO)-Gary Patton (who also served as head of the IBM Microelectronics Division) joined Intel Corp in 2019, and Intel Corp prepared the elements needed to apply the design to a specific process node (Process Node).

It is said that Patton is responsible for R & D management in the direction of Process Design Kit (PDK), IP (Intellectual Property), Tool and so on.

The best thing about Intel Corp is not the 10-nanometer process.

Intel Corp will continue to improve the level of technology in the future. As two optimized versions of the 10nm process, it is planned to launch 10nm + in 2020 and 10nm + in 2021.

Mr. Mark Bohr, a former senior researcher (Senior Fellow) of Intel Corp and director of the process Architecture (Process Architecture) & Integration department, said in 2017 that Intel Corp's 10nm + transistor has a performance better than 10nm, but a frequency of less than 14nm +, so it is not an attractive product for the CPU of the desktop game console PC.

Considering that 10nm has the problem of high defect density, similarly, the frequency problem is also one of the most priority problems for 10nm +.

Intel Corp plans to mass-produce 10nm + + transistors with significantly improved performance in the second half of 2020. At that time, for applications (Application) with higher clock frequency (Clock Rate) advantages, 10nm + + will be a good choice. On the other hand, Intel Corp himself admitted that the profit of 10 nm process products is less than 22 nm and 14 nm.

In early 2020, George Davis, Intel Corp's CFO, said, "10nm should not be Intel Corp's most powerful technology node." Compared with 14 nm and 22 nm, the yield of 10 nm is lower, but we are working to solve this problem. In addition, we plan to start the 7nm era by the end of 2021, and the performance of 7nm will be much more than 10nm.

Dreamy Cannon Lake

Intel Corp's Cannon Lake processor was originally scheduled to hit the market in the second half of 2016, but was delayed to the second half of 2017 and limited shipments in 2018. The only Cannon Lake- we know of, "Core i5-8121U (no built-in GPU)", did not hit the mass market and ended production "quietly" in early 2020.

It is believed that: "from the second half of 2017 to the first half of 2018, Intel Corp's 10nm has been full of twists and turns, so Intel Corp has to make a substantial transformation and redesign of the 10nm process. The evidence is that there is only one SKU (Stock Keeping Unit) for the product shipped.

Intel Corp's 10-nanometer product, Ice Lake, went on sale in mid-2019 and now has 11 Semi-custom SKU models on sale. Ice Lake has a wide range of operating frequency and TDP (Thermal Design Power) (9W~28W), which proves that Intel Corp can successfully produce 10nm chips with great advantages in performance and power consumption.

In order to obtain higher performance and higher yield, Intel Corp must use the improved version of 10nm technology.

Unlike the system equipped with Cannon Lake, the PC with Ice Lake has been put on the market by almost all manufacturers, so Intel Corp improved the supply of 10nm chips from 2019 to 2020.

On the other hand, Intel Corp will use 14nm processor technology-"Comet Lake" to be used in mainstream notebook computers, high-performance notebook computers and desktop game computers.

It is not surprising that 14nm + + processors are applied to game console devices (I hope readers will pay attention to the fact that Intel Corp has optimized this technology to adapt to higher clock rates). From the two points that apply Comet Lake to mainstream notebooks and notebooks equipped with Ice Lake are in short supply, we can see that the supply of Intel Corp's 10nm processors may not be sufficient in the second half of 2019 and the first half of 2020.

10nm +-- the release of "Tiger Lake"

After Ice Lake, Intel Corp announced the "Tiger Lake" processor on "CES2020". At the same time, Intel Corp also said that more than 50 computers with "Tiger Lake" would be put on the market before the next long holiday (Holiday Season).

Intel Corp's 10nm products are slowly increasing step by step, in addition to CPU, there are also 10nm-based FPGA "Agilex", 5G direction SoC "Atom P5900 series" and so on. The Atom P5900 has received design proposals (Design-win) from three communications equipment manufacturers.

But not everything is so optimistic. Intel Corp has postponed the shipment of the 10 nm + "Xeon (R & D Code: Ice Lake)" processor from the first half of 2020 to the second half of the same year.

This should also have an impact on Intel Corp's server-oriented business. Although we have no way to speculate the reason for the delay, it is not difficult to imagine that if the defect density is high, it will have a greater impact on large chips than small chips.

Although mainstream laptops can "tolerate" the defect density and yield of 10 nm +, they still fail to reach the required level of high-end servers.

To understand the production of Intel Corp's 10nm chips, it is necessary to understand how many 10nm wafers Intel Corp can handle and how many factories can handle 10nm wafers. Recently, Intel Corp has not released much information about its production capacity. However, it is not without mentioning it. Intel Corp has announced that factories in Arizona, Oregon and Israel in the United States can produce 10-nanometer chips.

Intel Corp made a big bet on 10nm and Hyper Scaling (super miniature), the delay of mass production of 10nm products, the adjustment of 10nm technology in Ice Lake, and Intel Corp spent billions to expand production of 14nm in order to meet the processor demand between 2018 and 2019.

Today, it is difficult to say that Intel Corp's 10-nanometer strategy has yielded results. In addition, Intel Corp believes that it is very difficult for shipments of 10-nanometer products to exceed 14 nanometers within 2020. In early 2020, it admitted that the profit of 10 nanometers was not as profitable as other previous processes.

Having said that, Intel Corp is, after all, a giant manufacturer with a large number of customers, so it is hard to imagine skipping 10nm and directly entering the next generation of node technology. There should be a lot of products using 10nm, 10Nm + and 10nm + in the future. Of course, we also look forward to Intel Corp's adoption of EUV lithography with 7 nm technology.