Simulation/storage/RF/flat panel display circuit design EDA full-process tools continue to gain strength. The company has now achieved coverage of full-process design tools in the field of analog circuit design, storage circuit design, RF circuit design and flat panel display circuit design: 1) In terms of simulation, as the only local EDA enterprise in China that can provide EDA tool systems for the entire analog circuit design process, the company's analog circuit design full-process EDA tool system includes schematic editing tools, layout editing tools, circuit simulation tools, physical verification tools, parasitic parameter extraction tools, and reliability analysis tools, etc., providing users with a one-stop shop from circuit to layout, design to verification A complete solution. 2) In terms of storage, during the 23-year reporting period, the company launched a new full-process EDA tool system for fully customized storage circuit design. The system includes storage circuit schematic editing tools, circuit simulation tools, rapid storage circuit simulation tools, storage circuit physical verification tools, storage circuit parasitic parameter extraction tools, and storage circuit reliability analysis tools, etc., providing users with a one-stop complete solution from circuit to layout and design to verification. 3) In terms of RF, the full-process design of silicon-based RF circuits can be achieved through the company's full-process EDA tool system for analog circuit design; during the 23-year reporting period, the company launched a new EDA tool system for the whole process of compound RF circuit design, forming a complete EDA tool system for the entire RF circuit design process. 4) In terms of flat panel displays, during the 23-year reporting period, the company launched RcExplorFPD TP, a parasitic parameter extraction tool for flat panel display touch panel design, and AetherFPD, an upgraded flat panel display circuit design schematic and layout editing tool.

The coverage of digital circuit design tools throughout the EDA process continues to increase. The company's digital circuit design EDA tools provide key solutions for some aspects of digital circuit design, including unit library characterization extraction tools, memory circuit characterization extraction tools, mixed-signal circuit module characterization extraction tools, unit library/IP quality verification tools, logic synthesis tools, timing power consumption optimization tools, high-precision timing simulation analysis tools, clock quality inspection and analysis tools, layout integration and analysis tools, large-scale digital physics verification, and large-scale digital parasitic parameter extraction tools. During the 23-year reporting period, the company launched a new logic synthesis tool, ApexSyn, which enables automatic synthesis from RTL design to gate-level network tables, scan chain circuit insertion, and optimization of design performance, area, and power consumption. At the same time, the tool supports a variety of Logic Ware design components, making the tool easier to use and improving the quality of intensive data path design results. Currently, the tool has been applied to many customers. During the 23-year reporting period, the unit library/IP quality verification tool Qualib obtained ISO 26262 TCL3 and IEC 61508 T2 international standard certification certificates, and can support chip designs with the highest ASIL D level of automotive safety integrity standards.

The goal of localizing the entire EDA process for wafer manufacturing/advanced packaging remains unchanged. At present, the company has formed multiple solutions in various segments of EDA in wafer manufacturing, including PDK kit development solutions, complete tool chain support solutions for basic IPs such as standard cell libraries and SRAM, lithographic mask data preparation and analysis verification solutions, physical rules verification, and manufacturability inspection solutions, etc., providing important tools and technical support for wafer manufacturers.

During the 23-year reporting period, the company launched five new tools, including GoldMask, a lithographic mask data processing and verification analysis platform, PCM, a parametric layout unit development tool PCM, an interface layout unit development tool PLM, TPM, an automated test chip layout generation tool, and PBQ, a PDK automated development and verification platform. In the layout design process of advanced packages, it is necessary to process a large number of high-density I/O (input/output) pins, which makes traditional manual wiring extremely time-consuming and seriously affects design efficiency. The company's advanced packaging automatic wiring tool Storm supports the industry's mainstream advanced packaging silicon-based technology and organic RDL (RedistributionLayer Heavy Wiring Layer) process, and realizes functions such as large-scale interconnect wiring between multiple chips, high-density escape wiring, and large-area power ground plane wiring.

Independent R&D+cooperative development+merger and acquisition integration to accelerate the full process layout and breakthroughs in core technology. By the end of '23, the company's R&D personnel accounted for 76% of the total number of employees, and R&D expenses were 685 million yuan, accounting for 67.77% of revenue, compared to +7pcts in '22.

The company will continue to increase investment in R&D, accelerate the pace of technological innovation, and enhance product market competitiveness to achieve short, medium and long-term goals. 1) Short-term goal: Focus on filling up the shortcomings of core EDA tool products in key aspects of integrated circuit design and wafer manufacturing, and at the same time strengthen the ability to support advanced processes of existing tools. Further increase research and development of core technologies such as design, simulation, and verification, and collaborate with the industry to achieve full process coverage of integrated circuit design tools and core tools for wafer manufacturing and packaging, and some products have reached the leading international level; 2) Mid-term goals: complete the development and marketing of integrated circuit design tool systems, fully realize the localization and replacement of design tools, and at the same time, more products reach the leading international level. Collaborate with the industry to achieve full process coverage of manufacturing, sealing and testing tools, and support the most advanced domestic technology; 3) Long-term goals:

The full-process localization and replacement of EDA tools in the field of integrated circuit design, manufacturing and packaging has been fully realized, and many products have reached the leading international level, making it a global EDA leader.

Investment advice

We expect the company to achieve revenue of 13.17/2.2 billion yuan in 2024/2025/2026, and realized net profit of 1.56/2.30/366 million yuan, respectively. The current stock price corresponding to 2024-2026 PS is 32 times, 25 times, and 19 times, respectively. This is the first coverage, giving it a “buy” rating.

Risk warning

Risk of technological innovation, product upgrade, risk of loss or shortage of technical personnel, risk of changes in industrial policy, risk of market competition, risk of international trade friction, risk of overseas operations.