From the 1960s to the 2010s, engineering innovations to shrink transistors doubled the number of transistors on a single computer chip about every two years, and Moore's Law led to a sustained increase in chip speed and efficiency.

10nm 、 7nm 、 5nm 、 3nm... These shrinking chip process figures are the core driving force behind the evolution of the overall performance of global electronic products. As the engineering of making smaller transistors becomes more and more difficult, or even impossible to solve, the capital expenditure and talent cost of the semiconductor industry are increasing at an unsustainable rate.

Handel Jones, CEO of International Business Strategy (IBS), said: "the average cost of designing 28nm chips is $40 million. By contrast, the cost of designing a 7nm chip is $217 million, the cost of designing 5nm equipment is $416 million, and the 3nm design will cost as much as $590 million. "

In terms of advanced process design costs, Semiengingeering, a well-known semiconductor technology research institution, has also calculated the cost of chips under different processes, of which the development of chips on 28nm nodes costs only $51.3 million, 16nm nodes need $100 million, and 7nm nodes need $297 million. When it comes to 5nm nodes, the cost of developing chips will reach $542 million. Data for 3nm nodes are not yet available, probably because 3nm is still in the research and development stage. The cost is difficult to estimate. But judging from this trend, the cost of 3nm chip research and development may be close to $1 billion.

According to Taiwan Semiconductor Manufacturing Co Ltd and Samsung, it is expected to enter the 3nm phase in 2022. It can be seen that the money-burning game of advanced chips is accelerating. According to IBS, the development of the 3nm process will cost between US $4 billion and US $5 billion, while the cost of building a 3nm production line is about US $150-20 billion. This figure also explains why Taiwan Semiconductor Manufacturing Co Ltd previously announced that the 3nm fab needs an investment of US $20 billion. And Samsung in order to enter the 3nm process, the money invested is no less than Taiwan Semiconductor Manufacturing Co Ltd, just from this point of view, many chip manufacturers do not have this strength.

Indeed, the R & D and production costs of the process have risen from generation to generation, and the high technical difficulties and R & D costs have stopped most chip foundry halfway up the mountain. In 2018, Groufonde, the world's second-largest contract manufacturer, was forced to abandon research and development of the 7nm process because of high R & D costs. At present, only Taiwan Semiconductor Manufacturing Co Ltd, Samsung and Intel Corp are still sprinting to the summit.

As the world prepares for 3nm and more advanced process nodes, this paper focuses on several key nodes in chip design and manufacturing to analyze why the cost of 3nm chips or advanced process chips is so high.

Why is the cost of advanced process chips so expensive?

According to the manufacturing process of the chip, it can be divided into the main industrial chain and the supporting industrial chain: the main industrial chain includes chip design, manufacturing and closed testing; the supporting industrial chain includes IP, EDA, equipment and materials. Among them, the high cost is mainly composed of manpower and R & D costs, streaming fees, IP and EDA tools licensing fees and so on. At the same time, the wafer factory investment, wafer manufacturing and related equipment costs involved in the chip manufacturing process will also be shared in the overall cost of the chip. The more advanced the process, the higher the cost.

• Foundry cost

According to CEST's model, a single 300mm wafer built on a 5nm node costs about $16988, and a similar wafer built on a 7nm node costs $9346. It can be seen that the foundry price of each wafer of the same size wafer 5nm process node is more than 7000 US dollars higher than that of 7nm.

It can be inferred that the cost of the wafer built on the 3nm node may reach about $30, 000, and the foundry cost will be further increased.

Another set of data also confirms this, and the cost price largely depends on the difference between the chip process and the size of the wafer. According to data provided by IC Insights, the difference between contract manufacturing income per 0.5 μ 200mm wafer (US $370) and that of ≤ 20nm 300mm wafer (US $6050) is more than 16 times. Even at the same 300mm wafer size, the cost difference between ≤ 20nm and 28nm process is double.

It can be seen that with the improvement of process nodes, the foundry cost of wafers increases greatly.

In addition, in addition to the fab construction and contract manufacturing costs, the daily operating costs of wafer manufacturers are not low (of course, this part has been shared in the contract manufacturing costs).

According to the data in Taiwan Semiconductor Manufacturing Co Ltd's corporate social responsibility report, Taiwan Semiconductor Manufacturing Co Ltd's global energy consumption reached 14.33 billion kilowatt-hours in 2019, compared with 14.664 billion kilowatt-hours of electricity for Shenzhen's 13.4388 million permanent residents in 2019. This shows how much electricity Taiwan Semiconductor Manufacturing Co Ltd consumes in a year.

Moreover, the higher the precision of the process, or the higher the accuracy of lithography equipment, the power demand will be proportional to the increase. According to Taiwanese media reports, in the case of 5nm, when Taiwan Semiconductor Manufacturing Co Ltd's 5nm chip was mass produced, the company's electricity consumption per unit product increased by 17.9% compared with 2019.

• Mask (Mask) cost

Mask, also known as light mask, light mask, etc., is a pattern transfer tool or master in the process of microelectronics manufacturing, its function is similar to the "negative" of traditional cameras, according to the graphics that customers need, through the lithography process, micron and nanometer fine patterns are engraved on the mask substrate, which is the carrier of graphic design and process technology.

According to IBS data, the cost of the mask used in the 16/14nm process is about $5 million, but when it comes to the 7nm process, the mask cost quickly rises to $15 million.

Also learned from Taiwan Semiconductor Manufacturing Co Ltd (IEDM 2019), from 10nm to 5nm, with the application of EUV lithography technology, the number of masks used has decreased, and the number of masks used in 5nm and 10nm processes is not much different.

However, when the number of masks is basically the same, the more advanced manufacturing process increases the total cost of the mask, which can reflect the rising average cost of the mask.

As reflected in the chip cost, the mask cost of each CPU is equal to the total mask cost / total output. If the overall output is small, the cost of the chip will be higher because of the mask cost; if the output is large enough, for example, hundreds of millions of shipments per year, the mask cost will be apportioned by huge production, which can greatly reduce the mask cost per CPU, making the CPU with the attribute of "more expensive process + larger output" lower than the CPU with "cheaper process + smaller production".

It can be predicted that when it comes to 3nm, the mask cost is expected to rise again, further increasing the cost of the chip.

• EUV lithography machine

As one of the core equipment in the chip manufacturing stage, the lithography machine is responsible for "engraving" the circuit pattern, and its precision determines the accuracy of the manufacturing process. Its principle is to print the designed chip pattern on the mask, then use the laser beam to pass through the mask and optical lens, expose the chip pattern on the silicon wafer with photoresist coating, and finally transfer the pattern on the mask to the chip photoresist coating.

With the development of the process, when it comes to 7nm and more advanced technology nodes, EUV lithography with shorter wavelength is needed to achieve a smaller process. ASML of the Netherlands is the only manufacturer in the world capable of manufacturing EUV lithography machines.

Taiwan Semiconductor Manufacturing Co Ltd introduced EUV equipment at 7nm +, but the number of layers is relatively limited; 6nm adds EUV layer and optimizes PDK (process planning toolkit); 5nm has full EUV capability. As the chip faces 3nm and more advanced technology, chip manufacturers will need a new EUV lithography technology with high numerical aperture EUV (high-NA EUV). According to ASML's financial report, they are developing a next-generation EUV lithography machine using high-NA technology, with higher numerical aperture, resolution and coverage, which will be 70% higher than the current EUV lithography machine.

But EUV lithography machines have always been very expensive, and in 2018, Semiconductor Manufacturing International Corporation and ASML signed an order agreement to order an EUV lithography machine for $120 million. This price is basically in line with the price of EUV lithography disclosed by PHOTRONICS.

According to the latest financial report of the second quarter of 2021 released by ASML, as of July 4, 2021, ASML shipped 16 EUV lithography machines this year, with sales reaching 2.4561 billion euros, with an average price of 153.5 million euros per EUV lithography machine.

Combined with the financial report data of ASML over the years (2018 / 2019 / 2020), we can see that the price of ASML's EUV lithography machine has increased from 104.5 million euros to 144 million euros year by year.

An EUV lithography machine costs more than $100m and is quite difficult to buy. Every time ASML launches a generation of EUV lithography machine, the production capacity of the new equipment is steadily increasing, but the price is naturally higher. It has been revealed that the second generation of ASML EUV lithography machine will be the NXE:5000 series, to further improve the lithography accuracy, originally planned for 2023, is now postponed to 2025-2026, and the price is expected to exceed 300 million US dollars.

Of course, in addition to the most expensive EUV lithography machine, the equipment and materials used in deposition, etching, cleaning and packaging are also expensive, and the cost is increasing with the development of the process.

• Research and development & manpower cost

Advanced manufacturing process not only requires huge construction costs, high R & D and labor costs also raise the threshold of design enterprises.

Chip design includes circuit design, layout design and mask fabrication, etc., which need to consider many factors and knowledge structure. Take the familiar 5G SoC as an example, industry manufacturers can integrate independent AI processing unit APU, multimode communication baseband, camera ISP, various control switches, microkernels and other self-research modules. This part of the cost is difficult to estimate specifically, and it belongs to the long-term R & D achievement, but the intensity of investment can be seen in the labor cost.

Manpower cost is an important part of R & D cost. The efficiency and quality of project development are related to the number and level of engineers. The annual salary of domestic senior chip design engineers is generally between 50-1 million yuan. It is understood that Cyrus mentioned when developing the FPGA chip of 7nm process codenamed Everest, that it took four years and 1500 engineers to develop successfully, and the project cost more than 1 billion US dollars. FPGA chips have been like this, and more complex high-end CPU and GPU chips require a huge amount of investment. NVIDIA Corp used 2000 engineers to develop Xavier, and the development cost has reached 2 billion US dollars.

The development cost of the chip depends on the chip size, chip type, etc., according to industry insiders, the most expensive designs (such as some high-end CPU) are higher than the data provided by IBS, while others (such as some ASIC) are much lower than IBS data. Generally speaking, with the variety and shape of chip design, and constantly changing, it is difficult to predict its specific cost.
On the other hand, the transition of transistor architecture to GAA is also increasing the cost of chips.

At present, with the continuous increase of aspect ratio, FinFET is approaching the physical limit. In order to produce chips with higher density, circumferential gate transistor (GAAFET) has become a new technology choice. Therefore, the transistor structure from FinFET to GAA has become the key to the continuation of Moore's Law.
Samsung, Taiwan Semiconductor Manufacturing Co Ltd and Intel Corp have all introduced the research of GAA technology, among which Samsung has already used GAA in 3nm chip design first. However, GAA still faces various challenges, including the imbalance of Namp p, the effectiveness of the bottom plate, internal spacing, gate length control and device coverage, etc.

In the process of scientific and technological change, new technologies need more time to develop, and new technologies and equipment are needed in all aspects, all of which are increasing the cost of chip development.

• EDA cost

EDA covers all the processes of integrated circuit design, verification and simulation, and almost all the uses, specifications, characteristics and fabrication processes of the chip are completed at this stage. Extremely complex circuit diagrams can be designed by using EDA tools, thus powerful chips can be manufactured.

According to ESD Alliance data, the global market size of EDA is 11.467 billion US dollars in 2020, which is relatively small compared to the chip market of hundreds of billions of dollars, but EDA plays a vital role in the efficiency and cost of chip design.

EDA is an industry with a small market but a long technical process, which requires a wide variety of software and hardware tools to cooperate with each other to form a tool chain. Take the EDA giant Synopsys as an example, there are more than 500 tool chains that completely cover the whole chip design process. According to the financial results of Synopsys and Cadence, the revenue in 2020 was $36.9 and $2.68 billion respectively, the two companies spent more than 35% on research and development each year, and the R & D cost of Synopsys reached an astonishing $1 billion, and the cost of EDA software development is accelerating.

According to Synopsys's latest earnings data, second quarter 2021 revenue of $1.0243 billion, semiconductor and system design, including EDA tools, IP products, system integration solutions and related services; software integrity, including security and quality solutions for software development. EDA's revenue reached $587.6 million, accounting for about 57 per cent.

According to online data, a 20-person R & D team costs $1 million a year for EDA tools to design a chip (including IP costs such as EDA and LPDDR). From the industry attribute of EDA and the high R & D investment, it can be predicted that when it comes to the 3nm process, the licensing fee for EDA tools is naturally even more expensive.

• IP Licensing cost

Semiconductor IP refers to those design modules that have been verified, reused, have certain deterministic functions and independent intellectual property functions in integrated circuit design. Chip companies can purchase IP to achieve certain functions (such as Cortex series CPU of ARM, GPU IP license of Mali series, etc.). Other small modules, such as audio and video codec, DSP, NPU..., etc., can also be purchased. This similar "building block" development mode can greatly shorten the development cycle of the chip, reduce the difficulty of chip design and improve performance and reliability at the same time.

Chip design is mainly due to the fact that the underlying architecture of the chip core (intellectual property rights and technical barriers) is in the hands of a small number of manufacturers, and the patent fee may reach more than 50% of the design cost. It is understood that in the past, ARM usually requires customers to choose a specific chip design and pay the license fee in advance. This model generally requires manufacturers to spend millions of dollars at a time to be allowed to use it (depending on the complexity of the licensed technology, usually between $1 million and $10 million), while royalties are paid to IP manufacturers at 1% of the final price of the chip after the chip is put into production.

On the other hand, according to Synopsys and Cadence performance data, Synopsys's revenue share of IP and systems integration increased from 28% in 2017 to 33% in 2020, reaching US $12.026 million, while Cadence's IP share rose from 11% in 2016 to 14% in 2020.

It can be seen that IP as the value node with the highest technical content, with the chip process becoming more and more advanced and the chip price rising, the difficulty of IP research and development and licensing costs will also increase.

Write at the end

Under the superposition of the above factors and links, the chip cost of the advanced process is naturally high.

The author can not accurately calculate and predict the cost and price of 3nm or any process node, but draw as objective a point of view as possible on the basis of collecting limited data. At the same time, I hope that based on this, we can better understand the reason why advanced technology brings a huge increase in chip cost.

At present, with the continuous development of semiconductor processes, the pace of Moore's Law slows down gradually. Chip cost has become an important factor hindering the development of advanced processes, but cost will never be the root cause. In the final analysis, money is only an auxiliary role.

Professor Hu Zhengming, inventor of FinFET technology, once said that there is a new crisis in the semiconductor industry about every 20 years. Twenty years ago, people were so pessimistic that they couldn't see how chips could perform better, consume less power, and control costs.

Now, the semiconductor industry may have come to the crisis cycle node of the 20-year cycle, what is needed to continue the vitality of Moore's Law is a breakthrough in innovative technology and equipment. When the advanced manufacturing process comes to 3nm, 2nm and 1nm, where will the future development of the semiconductor industry be?