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Recently, the increasingly popular heterogeneous and multi-die 2.5D packaging technology has promoted the emergence of a new type of interface, that is, ultra-short reach (ultra-short reach: USR), whose electrical characteristics are very different from the traditional PCB wiring. Long and lossy connections require the use of SerDes IP's serial communication channel, while short-haul interfaces support parallel bus architecture.

SerDes signals need to be terminated (50 ohm) to minimize reflection and reduce far-end crosstalk, thereby increasing power consumption. The electrical short-circuit interface in the 2.5D package does not need to be terminated. Compared to the clock "recovering" embedded in the serial data stream, and with the associated clock data recovery (CDR) circuit area and power supply, these parallel interfaces can use a simpler "clock forwarding" circuit design so that the clock signal that provides transmission carries a set of N data signals.

Another advantage of this interface is that it is greatly reducedChipBetween the electrostatic discharge protection (ESD) circuit design requirements. The internal package connection will have lower ESD voltage stress constraints thus saving a lot of I / O circuit area (and significantly reducing the I / O parasitic effect).

The unique interface design between bare chips in 2.5D packaging requires the driver to use a "small chip" because the full-chip design overhead of SerDes links is not required. However, so far, there have been many circuits and physical implementations for these USR interfaces.

In the invited speech of the recent VLSI 2020 seminarTaiwan Semiconductor ManufacturingPut forward their proposal about parallel bus, clock forwarding architecture "LIPINCON", which is the abbreviation of "low-voltage, in-package interconnect". This article briefly reviews the focus of the presentation.

The key parameters of short distance interface design are:

Data rate of each pin: depending on wire length / insertion loss, power consumption, required circuit timing margin

Bus width: with modularization to define subchannels

energyEfficiency: in pJ / bit, including not only I / O driver / receiver circuits, but also any other data prefetch / queuing and / or encoding / decoding logic

"Beachfront" (linear) and area efficiency: measure the total data bandwidth of each linear edge and area perimeter on the small chip, namely Tbps / mm and Tbps / mm * * 2; depending on the signal bump spacing, and the number and spacing of metal redistribution layers on the 2.5D substrate, it defines the number of bump rows that can route the signal trace-see the following figure

Latency: another performance indicator; the time between initiation and reception of data transmission, measured in "unit intervals" of the transmission cycle

Architects are looking to maximize the total data bandwidth (bus width * data rate) while achieving very low power consumption per person. These key design measures apply regardless of whether the small chip interface is between multiple processors (or SoC), processor-to-memory, or processor-to-I / O controller functions.

The implementation of physical signals will be different, depending on the packaging technology. A 2.5D packaged signal RDL with a silicon intermediary layer will take advantage of the finer metal spacing available (for example, TSMC's CoWoS). For multi-chip packages using recombinant chip substrates to embed chips, the RDL layer is much thicker and spaced (for example, the InFO of TSMC). The following figure illustrates typical signal wiring shielding (and unshielded) associated with CoWoS and InFO designs, as well as the corresponding signal insertion and remote crosstalk losses.

The following figure schematically illustrates the key features of Taiwan Semiconductor Manufacturing Co Ltd's LIPINCON IP definition.

A 0.3V low signal swing interface (also saves power) is adopted.

The data receiver uses a simple differential circuit with a reference input to set the switch threshold (for example, 150mV).

The clock / strobe signal is forwarded with the data signal (subchannel); the receiver uses a simple delay locking loop (DLL) to "lock" the clock.

In short, DLL is a unique circuit that consists of even chains of the same delay unit. The following figure shows an example of a delay chain. The switching delay of all levels can be adjusted dynamically by modulating the voltage of series nFET and pFET devices input into all levels of input inverter (that is, "insufficient current" inverter). (other delay chain implementations dynamically modify the same capacitive load on the output of each stage, rather than adjusting the internal transistor drive intensity of each stage. )

The "loop" in DLL is formed by a phase detector (XOR logic with a low-pass filter) that compares the input clock with the final output of the chain. The leading or lagging characteristic of the input clock relative to the chain output can adjust the inverter control voltage. Therefore, the total delay of the chain is closely related to the input clock. The (equal) delay at each stage of the DLL chain provides an output corresponding to a specific phase of the input clock signal. Capture parallel data in the receiver trigger using the appropriate phase output, which is a way to compensate for any data offset to the clock on the interface.

Taiwan Semiconductor Manufacturing Co Ltd's IP team developed an innovative approach for the specific situation of SoC to memory interface. Memory chips do not necessarily need to be embedded in DLL to capture signal input. For very wide interfaces-for example, dividing 512 addresses and 256data bits into subchannels-the overhead of DLL circuits in cost-sensitive memory chips can be high. As shown in the following figure, the DLL phase output appears in the SoC, which is used as the input strobe pulse of the memory write cycle. (the figure also shows the memory read path, which illustrates how to connect the data strobe pulse from the memory to the read_DLL circuit input. )

For parallel LIPINCON interfaces, simultaneous switching noise (SSN) related to signal crosstalk is a problem. For the above CoWoS and InFO RDL signal connections, the results given by TSMC show that the crosstalk of this low swing signal is very easy to manage.

To be sure, designers can choose to develop logical interfaces between small chips that use data coding to minimize signal conversion activity in continuous cycles. The easiest way is to add a data bus inversion (DBI) code so that the data in the next cycle can be compared with the current data and transmitted using real or inverted values to minimize switching activity. An additional DBI signal between the small chips sends this decision to the receiver to decode the value.

The development of heterogeneous 2.5D packaging depends on the integration of known high quality chips / small chips (KGD). However, the assembly yield of the final package can be improved by adding redundant channels, which can be selected after package testing (ideally built-in self-test). Taiwan Semiconductor Manufacturing Co Ltd's presentation includes examples of redundant channel topologies that can be integrated into a small chip design. The following figure illustrates two architectures for inserting redundant silicon through holes (TSV) into the interconnect. When designing the interface between small chips, this will be a tradeoff between package yield and circuit overhead.

In the SerDes-based design, the complete circuit and PCB interconnection extraction and simulation are used to analyze signal loss. The changes of signal jitter and amplitude are analyzed according to the voltage difference of the receiver sensing amplifier. Hardware lab-based probes have also been carried out to ensure that the appropriate "eye opening" ("open eyes") at the receiver is performed to capture data.

Taiwan Semiconductor Manufacturing Co Ltd stressed that this kind of interface verification is not feasible for 2.5D packaging technology. As shown in the figure below, their IP team developed a novel method of introducing variants into LIPINCON send drivers and receive capture circuits to create equivalent eye maps for hardware verification.

Taiwan Semiconductor Manufacturing Co Ltd's speech mentioned that some of their customers have designed and developed their own IP implementations for the USR interface. An example shows a very low swing (0.2V) electrical definition that is "ground-based" (for example, signal swings above and below the ground).

However, for non-wafer customers who seek to use advanced packaging but do not have the design resources to "develop" chip interface circuits, the TSMC LIPINCON IP definition is an attractive choice. And, frankly, given the support Taiwan Semiconductor Manufacturing Co Ltd can provide, the definition may help accelerate "standard" electrical definitions among developers looking to capture opportunities in the IP and small chip design market.

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