If the clock is turned back a year, it remains somewhat uncertain who will first break through in the competition of 2nm wafer foundry.$Taiwan Semiconductor (TSM.US)$Since dominating the market after 7nm, the leading wafer foundry has not faced this many "threats" in a long time.

On one side, Samsung vows to surpass Taiwan Semiconductor and become number one in the world; on the other side, Intel is raising the flag of "four years, five nodes," hoping to quickly surpass Taiwan Semiconductor in the coming years; additionally, the long-dormant Japanese semiconductors also hope to regain their peak with Rapidus. Among them, 2nm has become a critical battleground and stronghold for these giants.

However, from the current situation, the outcome of this "great war" surrounding 2nm seems to have been determined, with Taiwan Semiconductor likely to be the sole winner.

Taiwan Semiconductor fires the first shot.

Recently, news regarding Taiwan Semiconductor's 2nm has been frequent.

Firstly, at the end of November, Taiwan Semiconductor's new 2nm plant in Kaohsiung held its equipment installation ceremony, setting three major records: firstly, it marks the establishment of Taiwan Semiconductor's first 12-inch factory in Kaohsiung, warming up for mass production in 2025; second, the plant started installing equipment over six months ahead of schedule; third, after mass production, the Kaohsiung plant will be connected with the new 2nm plant in Hsinchu Baoshan, producing the most advanced chips in the world.

Secondly, prior to today, there were reports that Taiwan Semiconductor has successfully trial-produced its 2nm process with a yield rate of 60%. According to sources in the supply chain, the trial production results at Taiwan Semiconductor's Baoshan factory in Hsinchu County, Taiwan, have exceeded expectations.

Thirdly, Taiwan Semiconductor has also claimed that it will begin mass production in 2025, and the demand is higher than for the 3nm wafers, with the only variable that needs to be addressed being the high cost.

Taiwan Semiconductor Chairman Wei Zhe-Jia pointed out in an earlier earnings report conference call that although high-performance computing (HPC) customers are shifting towards small chip designs, this trend has not diminished the demand for 2nm technology. On the contrary, customer inquiries have surged, with the demand for 2nm surpassing that for 3nm, and the expected production capacity could be even higher.

In facing the issue of high costs, earlier reports indicated that the cost for each 2nm wafer from Taiwan Semiconductor is as high as $30,000. Regarding this issue, **** media stated that the semiconductor giant has found a way to lower this figure, known as the 'Cyber Shuttle' service. It allows existing customers to evaluate their chips on the same test wafer, thereby reducing costs. The so-called Cyber Shuttle refers to wafer sharing, enabling Taiwan Semiconductor's customers to save a substantial amount on design and mask costs while also accelerating the testing production process.

Although it is unknown how much Taiwan Semiconductor's 2nm Cyber Shuttle can reduce costs, it appears that several manufacturers are already interested in Taiwan Semiconductor's 2nm technology. Related reports suggest that Apple and Advanced Micro Devices are expected to become the first customers of Taiwan Semiconductor's 2nm.

According to reports, Apple’s 2nm chips are expected to start tape out in December 2024, which includes the Apple A20 Pro and Apple M5. The former is set to begin mass production by the end of 2025, while the latter will have to wait until the second quarter of 2026.

As for AMD, related reports indicate that AMD will use 2nm for the company's Zen 6 series desktop CPUs and CDNA 5 M1400 AI accelerator. Earlier rumors suggested that Zen 6 will use a hybrid process of 3nm and 2nm, similar to Intel's approach with Meteor Lake. If the news is accurate, AMD could reduce costs by manufacturing only CCD on N2 while producing the remaining components on more mature nodes.

Intel,$NVIDIA (NVDA.US)$It will also turn to Taiwan Semiconductor to utilize its 2nm technology.

First, let's look at Intel. After successfully utilizing Taiwan Semiconductor's N3B to achieve the CPU module of Lunar Lake, Intel plans to continue collaborating with Taiwan Semiconductor to develop its cutting-edge nodes. This will extend to its Nova Lake desktop chip series scheduled for release in 2026. However, we must also see that Intel may still shift Nova Lake to its internal 14A node. Given that this chip has not yet been taped out, it is still too early to make predictions. The tape-out is planned to be completed by mid-2025 and will decide the fate of Intel's next-generation desktop platform.

As for NVIDIA, their N2 order placed with Taiwan Semiconductor mainly revolves around 'Rubin next', which is the successor to the Rubin platform announced by the company at the 2024 Taipei International Computer Show. However, these chips are not scheduled to tape out until 2026, with mass production starting in 2027. Moreover, the successor to NVIDIA's Blackwell (RTX 6000) series is very likely to continue using N3 derivatives.

In addition,$Broadcom (AVGO.US)$Soxih and Bitmain are also expected to use chips manufactured on Taiwan Semiconductor's N2 to produce ASICs. MediaTek is also on the list, with its 2nm chips expected to launch in mid-2025 and enter mass production the following year. However, Bitmain's future is still uncertain due to some well-known factors.

From the above, it can be seen that these well-known fabless companies mostly choose Taiwan Semiconductor as their first choice, which is also why we believe that '2nm, the winner has been decided.'

Samsung is deeply troubled.

As the closest competitor to Taiwan Semiconductor in recent years, Samsung has also been working hard in wafer foundry. Earlier, they announced that Japanese AI Chip company Preferred Networks (PFN) would become the first customer for their 2nm technology. In recent years, they have made significant investments in Automotive Chips.$Ambarella (AMBA.US)$They also selected Samsung's 2nm for production outsourcing of their new products.

However, there has been a continuous stream of bad news regarding Samsung's 2nm technology. In addition to rumors of poor yield rates, some insiders have even indicated that Samsung's self-developed mobile chip may consider Taiwan Semiconductor's processes. The bearish impact on the South Korean chip giant is evident. From the recent changes and statements from Samsung's leadership, it seems that the yield rate of the 2nm process is also a concern for them.

Because of this deep concern, Samsung has made personnel changes, appointing Han Jin-man as the company president and head of its wafer foundry business. Additionally, Samsung has appointed Nam Seok-woo, the company's chip factory engineering and operation chief, as the technology head of the wafer foundry business.

Han Jin-man, the newly appointed head of Samsung's chip foundry business, stated on Monday that he would do his utmost to improve the company's advanced 2nm chip processing technology and strive for more customers to compete against foundry rival Taiwan Semiconductor. During his speech to employees upon taking office as head of the foundry business, Han Jin-man expressed his intention to implement a 'dual-track strategy' to narrow the technological gap between Samsung and Taiwan Semiconductor, and defend against competition from China.$SMIC (00981.HK)$Competition among fast followers.

Han Jin-wan admitted: "Although Samsung was the first to transition to the Gate-All-Around (GAA) process, there are still significant flaws in commercialization," he emphasized, "Rapidly expanding the production of the 2nm process is the company's top priority. We must acknowledge that we are behind our competitors, but we will overcome this challenge," Han Jin-wan further pointed out. "We will focus on significantly improving the yield of the 2-nanometer (nm) manufacturing process. Our goal is to achieve tangible changes by next year," Han Jin-wan concluded.

Although Samsung is irreplaceable, Samsung's foundry is also intensifying the construction of production facilities for mass production of the 2nm process. The company has been introducing various equipment for its Hwaseong factory's foundry line 'S3' to establish a 2-nanometer production line, aiming to install a production line with a monthly capacity of 7,000 wafers before the first quarter of next year.

Starting in the second quarter of next year, Samsung also plans to install a 1.4-nanometer production line at its Pyeongtaek 2 factory's 'S5', with a capacity of approximately 2,000 to 3,000 wafers per month. The remaining 3nm production line of S3 is scheduled to be fully converted to a 2nm production line by the end of next year. This move is part of a broader strategy of Samsung to advance its technology roadmap, aiming for mass production of 2 nanometers next year.

Samsung's new foundry head will also be responsible for the competition.$Qualcomm (QCOM.US)$、 $Advanced Micro Devices (AMD.US)$ With companies like NVIDIA as clients. Samsung has also stated that its goal is to switch to more advanced 1.4-nanometer chip processing technology by 2027.

However, while Samsung is desperately trying to catch up with Taiwan Semiconductor, they also face competition from Chinese manufacturers. Industry observers point out that the market share gap between Semiconductor Manufacturing International Corporation and Samsung has narrowed from 5.8 percentage points in the second quarter to 3.3 percentage points in the third quarter. The quarterly losses in Samsung's foundry division exceeded 0.7 billion USD, and the gap with Taiwan Semiconductor has also widened. To improve profitability, Samsung intends to expand its customer base in mature processes like the 10-nanometer.

Taiwan Semiconductor's Morris Chang recently admitted: "The reason why Samsung's foundry business is in this situation is mainly due to technical issues, not policy strategy issues."

Intel appears slightly confused.

Originally, under Pat Gelsinger's leadership, Intel was full of confidence in the 'four years and five nodes' initiative.

Shortly after taking office four years ago, Gelsinger vowed to establish a foundry to compete with Taiwan Semiconductor and promised to develop five manufacturing nodes within five years. Over the past few years, he has repeatedly expressed the view that Taiwan Semiconductor can be beaten. For example, in April of this year, former Intel CEO Pat Gelsinger stated that the company would be able to defeat Taiwan Semiconductor Manufacturing Company in semiconductor chip production.

Gelsinger stated at the Semafor Global Economic Summit that Taiwan Semiconductor has 'done an excellent job' and added that Intel 'helped create some of the technologies.' "Ten years ago, we made strategic decisions that were wrong, and they adopted some of those technologies and became the world's foundry." Gelsinger continued.

In Gelsinger's view, Taiwan Semiconductor's success is entirely due to strong support from Taiwan; therefore, he believes that the U.S. CHIPS and Science Act can similarly promote the development of domestic chip manufacturing, doubling output by the end of this century. However, the eagerly anticipated 18A process node (equivalent to 2nm) has been facing delays. Several rumors also indicate that one of its early customers, Broadcom, reportedly also has yield issues. Only 20% of the chips passed the early tests.

Looking back to last year, former Intel CEO Kissinger stated in an interview that Intel's 18A process is extremely advanced, and even competitors cannot compare their products to it. One important reason is that Intel has adopted the RibbonFET architecture, a technology that competitors have not yet utilized, allowing Intel's 18A and 20A processes to be more advanced than Taiwan Semiconductor's 2nm process.

As the final node of its ambitious '4 years and 5 nodes' roadmap, the twin 20A/18A represents a culmination of several new technologies, primarily Intel's realization of GAAFET (RibbonFET), which is combined with Intel's backside power delivery network (BS-PDN) technology PowerVia. The 20A represents an early version for this node, while the 18A is an improved version meant for long-term internal use and is also Intel's first major external node for its foundry.

Intel had previously revealed that there are already many potential customers for its 2nm foundry services, such as $Microsoft (MSFT.US)$ the U.S. Department of Defense, etc. By mid-2025, eight 18A chips are expected to complete tape-out, including products from Intel itself and external customers. However, various current reports suggest that Intel's 18A may not meet expectations.

According to Intel's original plans, the company expects its 18A to achieve manufacturing readiness in the second half of 2024, with Intel's commercial version of the 18A anticipated to further expand its competitive advantage in the first half of 2025. Recently, regarding the issue of low yield rates, both Intel and the now-dismissed Pat have been defending their position.

However, the current situation suggests that Intel still faces significant challenges. Relevant data indicates that Intel's operating loss in 2023 was $7 billion, an increase of over $2 billion from the previous year, indicating that Intel has much work to do to turn the situation around. According to Intel's planning, the company's goal is merely to achieve break-even in this division by 2027. Therefore, Intel has been raising billions of dollars in financial support to ensure that its multiple process node plans can be completed on time and produce sufficient quantities of chips.

However, with Kissinger's departure, this strategy has come under new scrutiny. Zhang Zhongmou bluntly stated: 'Intel's fatal flaw is the lack of a new strategy, and it has missed AI opportunities due to overly rushing into the foundry service (IFS). Now it faces a dual deficiency (lack of a new strategy and a new CEO).' This indeed poses a challenge for Intel.

The Chairman of Powerchip, Huang Chongren, summed it up with one sentence: “Intel cannot compete with Taiwan Semiconductor, that’s all there is to it.”

Written at the end.

As mentioned at the beginning of the article, Japan's Rapidus originally had high hopes for 2nm, and the company has also received a commitment for collaboration on 2nm from the company where Jim Keller is located. Atsuyoshi Koike, the president of Rapidus, also pointed out that apart from the already disclosed companies, Rapidus is negotiating with another 40 companies.

Recently, scientists from IBM and the Japanese chip manufacturer Rapidus jointly announced that they have achieved a key milestone in the continued development of 2-nanometer process chips. They used two different strategies to selectively reduce nanosheet layers, advancing the technology from single nanowires to stacked nanosheets. Nanosheets have better electrostatic control compared to nanowires and can accommodate more transistors within a given footprint. Nanosheet gate transistors also have multiple threshold voltages (or multi-Vt), allowing the chips to perform complex calculations without requiring excessive energy. The team found that they could do this without the metal gate boundary issues often associated with this construction method.

This means that the team has now taken an important step toward the first iteration of next-generation microchips. However, with both Intel and Samsung unable to challenge, what are the odds for Rapidus? The answer is evident!

Meanwhile, Taiwan Semiconductor's dominant position has raised concerns about the pricing power of 2nm. As foreign media have stated, in the absence of viable competition, Taiwan Semiconductor has transformed from an 'effective' leading monopolist to a true monopolist. This allows them to raise prices at will. Through calculations, it will soon be revealed that many companies designing cutting-edge chips today will have to deviate from Moore's Law curve, as it is no longer economically viable.

For example, suppose there is a sizable customer of Taiwan Semiconductor—not among the top three but possibly in the top ten. They might currently pay Taiwan Semiconductor $20,000 per wafer, while clients with lower yields pay close to $25,000. Assuming this company has a 170-square-millimeter chip, a convenient semi-analytical chip yield calculator shows 325 chips per wafer, or $61 per chip. If this company prices the chip at $140, their gross margin would reach 55%, which is decent but not amazing.

Now, suppose Taiwan Semiconductor raises the price of its next-generation process to $40,000. The estimated improvements in N2 density are still increasing, but let's assume the number of chips per wafer (375 KGD) increases by 15%. However, the cost per chip jumps to $107. This is the crux of the slowdown in Moore's Law—density increases are now significantly lagging behind price hikes. If design companies cannot pass the increased costs onto clients and the price is stuck at $140, the gross margin would fall to 22%, which is not good.

We can discuss to what extent chip designers can pass these costs onto their customers based on these numbers, but the conclusion remains the same: as Taiwan Semiconductor raises prices, producing cutting-edge chips is becoming increasingly unfeasible for more and more customers.

Of course, Taiwan Semiconductor will not infinitely raise prices and cut off all demand, but their pricing will maximize their own value extraction. This could significantly reduce the number of customers who can afford cutting-edge chip designs.

But in the future, who knows?

Editor/new