On December 12, according to the "Star Daily" (Reporter Guo Hui), at the Shanghai Integrated Circuit 2024 Annual Industry Development Forum and the China Integrated Circuit Design Exhibition (referred to as: ICCAD 2024) held yesterday (December 11), Wei Shaojun, chairman of the Integrated Circuit Design Branch of the China Semiconductor Industry Association, reviewed and evaluated the overall development of the chip design industry in 2024, stating that the domestic chip design industry sales are expected to reach 646.04 billion yuan in 2024, an increase of 11.9% compared to 2023, returning to a double-digit high-speed growth trajectory, and the proportion of the global integrated circuit product market is expected to remain basically stable compared to the previous year.

Wei Shaojun stated in his report that Technology is the foundation for chip design companies to survive. There is a need to continuously deepen traditional design technology, broaden, deepen, and thicken the foundations, establish a complete set of processes and methodologies suitable for their products in design methodology, and enhance contacts with manufacturing companies.

"It is gratifying to see that some leading chip companies have acquired COT (Customer Own Technology) capabilities. Their relationship with manufacturing foundries is no longer a simple outsourcing relationship but instead a technical partnership; more and more manufacturing companies are establishing new relationships with design companies. There is reason to believe that the model of mutual cooperation and progress will become mainstream in the development of the semiconductor industry in China," said Wei Shaojun.

"DTCO (Design Technology Co-Optimization) has already pointed out the direction of industry development." Wei Shaojun further stated that he hopes domestic design companies can break out of the framework of the design link and fully collaborate with manufacturing companies to enhance product R&D capabilities.

Notably, DTCO also became a core keyword in the speeches of relevant heads from foundries such as Taiwan Semiconductor, Samsung, and IP vendors like Arm Technology and Verisilicon Microelectronics (Shanghai) Co., Ltd., as well as EDA vendors Siemens and Hongxin Micro-nano at the Shanghai Integrated Circuit 2024 Industry Development Forum on December 11.

What is the DTCO methodology? What is the significance of discussing DTCO currently? What are the practical prospects? Regarding this, the "Star Daily" interviewed industry insiders and compiled reports.

The concept of DTCO is gaining traction, with both Taiwan Semiconductor and Samsung discussing it.

The general manager of Taiwan Semiconductor (China), Luo Zhenqiu, stated in a speech that Semiconductor technology will enhance computing power and energy efficiency in the future through three aspects: first, miniaturization technology, which will increase transistor density; second, DTCO/STCO (system technology collaborative optimization), which mainly promotes the collaborative optimization of design and process; third, 2.5D/3D advanced packaging and silicon stacking, further achieving system integration.

DTCO is the result of collaboration between the process development and design Industries. Luo Zhenqiu mentioned that during chip miniaturization, the proportion of optical technology miniaturization increasingly decreases, while the proportion provided by DTCO increasingly increases. "In the 7nm process, DTCO contributes more than 20% to transistor miniaturization, while at 3nm, the contribution rates of DTCO and optical miniaturization are almost identical. Based on this system, if optical miniaturization encounters a bottleneck in the future, DTCO can assist chip design in further reducing product size."

Song Zhexie, general manager of Samsung Semiconductor Foundry in Greater China, stated in his speech that low energy consumption, high performance, and high bandwidth are the three major technological innovations pursued by Foundry in design and process technology. To achieve this goal, Samsung Foundry has two technical routes: one is the innovative route of transistor structure; the other is the low-power differentiated route of FDSOI.

Furthermore, Song Zhexie mentioned that Samsung Semiconductor also has DTCO, which is design and process collaborative optimization, to further achieve optimization in PPA (Power, Performance, Area). First, in terms of area, Samsung Semiconductor can optimize design from cell level to block level through DTCO, reducing chip area; second, in terms of performance, DTCO optimizes parasitic resistance and capacitance, reducing RC delay; and in terms of low power consumption, DTCO can improve SRAM circuits, optimizing SRAM's Vmin. Samsung Semiconductor aims to enhance overall process performance through deep collaboration with Fabless, EDA, IP, and even equipment companies.

Taiwan Semiconductor and Samsung Semiconductor previously had iconic collaborative cases in the DTCO solution. It has been learned that Samsung announced a partnership with Synopsys in June this year to optimize the 2nm process; Taiwan Semiconductor also collaborated with AMD at the 2nm node to break through technical bottlenecks in chip performance and efficiency through DTCO collaboration, shortening development cycles and reducing costs.

The mainland market is more defined by EDA companies for DTCO.

DTCO seeks integrated optimization through the collaboration of design and process technology, improving efficiency, power consumption efficiency, transistor density, yield, and cost. In the IDM era, DTCO can be considered a standard methodology; the subsequent division of labor in industrial development has led to the success of Fabless and Foundry, which means that the DTCO concept exists mainly in some leading IDM companies.

"DTCO is actually a very old concept; the first time it was heard was at least four or five years ago. This year, it has been increasingly mentioned by large companies due to the complexity of chip design and tools, which require systematic consideration of subsequent processes from the design stage." A representative from a Chiplet chip product company told the Star Daily that, therefore, in the mainland market, the process of defining DTCO is now more often conducted by some EDA companies.

Including the wafer fab, different companies in the Industry Chain have varying understandings and corresponding methods of DTCO.

Wang Yucheng, the CTO of Hongxin Microelectronics, mentioned in a forum speech that DTCO is an important part of process evolution, and layout routing tools are a key aspect of DTCO.

In the view of Li Hongjun, CEO of Lingxian Pavilion Chip Technology, DTCO technology must include two components: one is process monitoring IP; the other is advanced process performance analysis Software. "Many excellent EDA companies in China are gradually improving the design process, but there is a core issue that has not been resolved, which is the lack of control over the analysis of advanced process technology, and the software lacks the functionality to analyze process data."

Yang Lianfeng, president of Concept Electronics, previously stated that at the beginning of the company's establishment in 2010, the idea of "yield-oriented design (DFY)" was clearly defined, and after more than a decade of development, DFY evolved into the "design-process collaborative optimization (DTCO)" method. Yang Lianfeng stated that under Moore's Law, the advancement of process platforms continuously increases the design/manufacturing risk and cost of chips, and to ensure the performance and yield of the final product, the industry has increasing demands for EDA/IP, and its importance and value have accordingly been continually enhanced, making DTCO essential.

The essence of DTCO: effectively enhance the process technology.

Li Hongjun, CEO of Lingxian Pavilion Chip Technology, stated in an interview with Star Daily that domestic industry's practices of DTCO are still in the early stages, leading to differing interpretations by EDA companies and fab factories based on tools and process perspectives.

"But DTCO should be understood more from the perspective of the demand side, that is, from the perspective of chip design companies. What chip companies need most is to improve chip performance and maintain stable mass production yield. Any method that can solve these two problems simultaneously can be called DTCO," said Li Hongjun.

Taiwan Semiconductor believes that the energy efficiency benefits brought by DTCO truly began to show from 7nm. However, at the Concept Electronics booth at the Shanghai Integrated Circuit 2024 Industry Development Forum, staff said to Star Daily that from mature processes to advanced processes, Concept Electronics' EDA tools support mainstream fab factories, and DTCO methods are also applicable to optimizing chip designs across different process nodes.

Lingyang Pavilion's Li Hongjun previously had over 20 years of design tape-out experience at Taiwan Semiconductor. He told the Star Daily that the typical performance improvement from one process generation update (such as from 14/12nm to 10nm) is about 15%. "Using the DTCO method effectively can improve performance by 30% in one go, equivalent to the advancement of two generations in process, meaning that 12nm can produce chips with performance comparable to 7nm, which is the essence of design process collaborative optimization."

Despite the promising prospects of the DTCO concept, sources from the mentioned chiplet chip companies noted, "In practice, implementing DTCO can be quite challenging. Firstly, it requires a higher degree of completeness in the EDA toolchain, and secondly, the new methods will change and challenge the working habits of engineers and architects in the design process."

Some industry insiders believe that the core issue for Chinese design firms lacking COT/DTCO capabilities is primarily due to a lack of scale. However, the growth in China's manufacturing and design markets is clear, with not only strong demand for high-end design and manufacturing but also rapid growth expected in memory IDM and specialized processes such as power semiconductors and CIS in the coming years. These factors provide a substantial market space for DTCO implementation.

As the DTCO methodology becomes more widely recognized, the re-convergence of semiconductor design and manufacturing may herald a potential reshaping of the industry landscape.