Taiwan Semiconductor has obtained Nvidia's agreement and will raise prices next year, with the 3nm process price possibly increasing by up to 5%, and the CoWoS packaging price increase ranging from 10% to 20%, the actual increase will depend on Taiwan Semiconductor's capacity expansion.

Previously, the chairman of Taiwan Semiconductor, Wei Zhejia, stated that the demand for CoWoS advanced packaging far exceeds supply, even though Taiwan Semiconductor has more than doubled its CoWoS production capacity this year. Advanced process and packaging technologies are key to the success of artificial intelligence (AI) chips. Citic Securities believes that advanced packaging technology is a significant development direction in AI foundational driving technology and has become a crucial production bottleneck. Currently, overseas front-end manufacturers lead globally, while back-end test manufacturers actively follow. Domestic enterprises are all making progress in this area.

According to the Financial Data Center, among related listed companies:

Shenzhen TXD Technology has mastered and accumulated key technologies such as Bump and FC in advanced packaging through the 'Kunshan Chip Gold Bump Full Process Packaging Test Project', and continues to research and develop key technologies such as silicon vias, rewiring, and hybrid bonding.

Jiangsu Dagang subsidiary Suzhou Keyang has mastered advanced packaging core technologies for wafer-level chip packaging such as TSV, micro-bumping, and RDL, including tin bumping, copper bumping, vertical through-silicon vias, and flip chip bonding.