Source: Science and Technology Innovation board Daily.
According to reports, Taiwan Semiconductor has formally established a FOPLP related team and planned to build a mini line for small quantity trial production; FOPLP uses large rectangular substrates instead of traditional circular silicon interposers, which can accommodate more I/Os; TrendForce predicts that the mass production time point of FOPLP applied to AI GPU is 2027-2028.
According to the latest report from MoneyDJ, Taiwan Semiconductor has officially established a FOPLP (Fan-Out Panel-Level Packaging) related team and planned to build a mini line for small quantity trial production.
It is reported that Taiwan Semiconductor plans to use rectangular substrates with dimensions of 515mm and 510mm in FOPLP, which can provide an area equivalent to more than three times that of circular substrates. Currently, the product will focus on the AI GPU field, with customers such as Nvidia and is expected to debut between 2026-2027.
Against the backdrop of growth in AI and other high-performance computing demands, FOPLP is expected to accelerate its entry into the AI chip field. FOPLP can accommodate more I/Os, has more powerful performance, and saves on electrical consumption. More importantly, it replaces traditional circular silicon interposers with large rectangular substrates, which have larger packaging dimensions and can improve area utilization rate and lower unit costs, thereby alleviating the shortage of CoWoS production capacity.
Early on, since Taiwan Semiconductor applied the FOWLP (Fan-Out Wafer-Level Packaging) technology to the iPhone 7's A10 processor in 2016, it has actively developed FOPLP solutions, but has been unable to make a complete breakthrough technically. In June this year, Taiwan Semiconductor also said that research on this technology was still in the early stages and might take "several years" to commercialize.
Some semiconductor industry insiders believe that because there were relatively few FOPLP players in the past, equipment suppliers tended to be conservative in their investments in this area, but with Taiwan Semiconductor officially joining, equipment suppliers' attitudes toward investment have become more proactive. In fact, this trend has already begun to show itself:
Last month, sources in the supply chain pointed out that Nanya is continuing to drive FOPLP and discussing related business with Nvidia and AMD.
Previously, there were also reports that Samsung is developing 3.3D advanced packaging technology for AI chips, with the goal of achieving mass production in the second quarter of 2026. The company has already introduced FOPLP for mobile or wearable devices.
For A-share listed companies, China Resources Microelectronics, Shennan Circuits, and Huahai Technologies have already entered the FOPLP-related business.
Research institution TrendForce Cinda Consulting's report this month pointed out that since the second quarter, chip manufacturers such as AMD have actively contacted Taiwan Semiconductor and OSAT manufacturers to use FOPLP technology for chip packaging. It is estimated that the mass production time points of FOPLP packaging technology in consumer IC and AI GPU applications may fall between the second half of 2024 and 2026, and 2027-2028, respectively.
However, some insiders believe that even if FOPLP goes into mass production, the probability of replacing CoWoS is not high. In the next 3-5 years, CoWoS will still be the mainstream advanced packaging process, while the leading 3D packaging SoIC will become Taiwan Semiconductor's main battlefield.
According to a June research report from Hua Jin Securities, currently Nvidia and AMD account for 80% of Taiwan Semiconductor's CoWoS production capacity. In addition, with the hot sales of new products such as the GB200 and the adoption of CoWoS technology by other companies such as Broadcom, there is a shortage of Taiwan Semiconductor's production capacity in the short term. Although FOPLP technology may not be superior to CoWoS on some performance indicators, its advantages in improving chip functional density, reducing interconnect lengths and restructuring system design, are in line with the benchmark requirements for chip performance in the era of artificial intelligence, making FOPLP expected to accelerate penetration in the AI chip field.
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