Incident reviews

On June 30, 2024, the groundbreaking ceremony for the multi-chip high-density board-level fan-out packaging industrialization project of Jiangsu Pangu Semiconductor Technology Co., Ltd. was held, marking that the project has entered the full construction stage. The project will focus on the development and application of board-level packaging technology.

Focusing on the development and application of board-level packaging technology, the annual output value of the project is expected to exceed 0.9 billion after delivery. According to Huatian Technology's “Notice Concerning the Establishment of Holding Subsidiaries and Related Transactions” of December 12, 2023, the total share capital of Pangu Company is 100 million yuan, of which Huatian Jiangsu invested 60 million yuan, with a shareholding ratio of 60%. The Pangu Semiconductor Advanced Packaging and Testing Project plans to invest a total of 3 billion yuan. The first phase of construction will be carried out in two stages. The first phase of construction will be from 2024 to 2028. A new plant with a total construction area of about 0.12 million square meters and related ancillary facilities will be built to promote the development and application of panel-level packaging technology. Partially put into operation in 2025, the project is expected to have an annual output value of not less than 0.9 billion yuan and an annual economic contribution of not less than 40 million yuan after delivery. Advanced packaging has received widespread attention in the industry to meet the packaging needs of miniaturization, lightness, low cost, high density, and high reliability in the artificial intelligence era. Wafer manufacturers, substrate companies, and packaging and testing companies have increased their investment in advanced packaging and have promoted the further development of advanced packaging technology processes. In recent years, board level packaging technology, as one of the important technology routes for advanced packaging, has received widespread attention from panel companies, substrate companies, and IDM companies. This technology eliminates substrates and frames in traditional packaging, is smaller in package size, can achieve heterogeneous integration of multiple chips, and at the same time significantly reduces manufacturing costs.

At present, many international giants have completed the layout and application of board-level packaging technology to achieve mass production, and the country is still in its infancy. Huatian Technology established Pangu Company to promote the development and application of board-level packaging technology in order to seize opportunities, seize market share, and enhance the company's competitiveness in future market competition.

The fan-out panel level package is based on the RDL process, which significantly increases the area utilization rate and reduces the cost by 66%. Fan-out panel level packaging (FOPLP) is an advanced packaging technology based on a rewiring layer (RDL) process that redistributes chips on a large panel and interconnects them, and can integrate multiple chips, passive components, and interconnects in one package.

FOPLP provides greater flexibility, scalability, and cost efficiency compared to traditional packaging methods. Fanout panel-level packaging can be understood as an extension of fan-out wafer-level packaging. It is a packaging technology derived from the need for multi-chip integration and further reduction in production costs. Therefore, fan-out board level packages have significant performance improvements and cost reduction advantages. Its high area utilization rate effectively reduces waste, and at the same time can process more chips in one packaging process, significantly improving packaging efficiency and forming a strong large-scale effect, thus having a strong cost advantage. Compared with the 300mm wafer-level package and the 515x510mm panel-level package, the panel-level package takes up 93% of the area, while the wafer-level package is only 64%, which directly causes a huge difference in production rate UPH during the production process. According to Yole data, FOWLP uses< 85%，FOPLP 面积使用率> 95% of the technical area, can place more chips, and is cheaper than FOWLP. The transition from 200mm to 300mm can save about 25% of the cost, and the transition from 300mm to the board level saves 66% of the cost.

Fan-out panel-level packages are mainly used in mid-range and low-end applications, and are gradually moving towards high-density wiring/small-pitch packages. Currently, fan-out wafer-level packaging in the industry is used in high-end applications with high I/O density and fine line width/line spacing, while fan-out board level packaging focuses on low- or mid-end applications with low I/O density and thick line width/line spacing. In this way, fan-out board level packaging can better utilize the cost advantage. Fanout panel-level packaging has broad application prospects in the fields of sensors, power ICs, RF, link modules, PMIC, etc. For example, about 66% of chips in automobiles can be produced using fan-out panel-level packaging technology, which is an excellent solution for automotive-grade chip manufacturing. With the development of board-level packaging technology, it is also gradually expanding to applications below 10um, and can further play a role in the high-density wiring and small-pitch packaging market.

Investment advice: We maintain our original performance expectations. We expect revenue of 13.02/15.393/17.283 billion yuan from 2024 to 2026, with growth rates of 15.2%/18.2%/12.3% respectively; net profit to mother of 0.592/0.91/1.283 billion yuan, respectively, with growth rates of 161.6%/53.6%/41.1%, respectively; corresponding PE is 43.7/28.5/20.2 times, respectively. As the development of artificial intelligence increases demand for computing power chips, it is expected to drive demand for advanced packaging. Based on the 3D Matrix platform, Huatian Technology can achieve high-density, high-reliability 3D heterogeneous integration of multiple chips by integrating technologies such as silicon-based fan-out packaging, bumping, TSV, C2W and W2W, adding to the company's continuous release of production capacity over 24 years and the cost advantages of future board-level packaging-related products. Its market share in the advanced packaging field is expected to continue to grow, maintaining the “building-A” rating.

Risk warning: risk of industry and market fluctuations; risk of international trade friction; risk of failure to industrialize new technologies, new processes, and products as scheduled; risk of production expansion falling short of expectations; risk of changes in supply and price of major raw materials/equipment; risk of impairment of goodwill, etc.