According to Nikkei Asia, Taiwan Semiconductor is exploring a new chip packaging method that will use rectangular substrates instead of circular wafers to improve production efficiency. The industry is expected to continue to increase packaging size in the future, accelerating the innovation process in the semiconductor industry.
According to Nikkei Asia, recently, Intel has been exploring a new advanced chip packaging method to cope with the rapidly increasing computing demand brought by artificial intelligence. Insiders revealed that the core of this new method is to use rectangular substrates of 510mm by 515mm, rather than the current circular wafers. This design allows more chipsets to be placed on each substrate, thereby improving production efficiency. The effective area of the rectangular substrate is more than three times larger than that of the circular wafer, and there is less unused edge area.$Taiwan Semiconductor (TSM.US)$Although this research is still in its early stages, if the news is true, it will mark an important technological shift for Taiwan Semiconductor. Previously, Taiwan Semiconductor believed that using rectangular substrates was too challenging. In order for this new method to succeed, Taiwan Semiconductor and its suppliers must invest a lot of time and effort in research and development and also need to upgrade or replace many production tools and materials.
Taiwan Semiconductor's current advanced chip stacking and assembly technology, such as the AI chip used for data centers, mainly relies on 12-inch silicon wafers, which is the largest size currently available. However, with the increasing size of chips and the demand for more integrated memory, the current industry standard 12-inch wafer may no longer be sufficient to meet the packaging needs of cutting-edge chips within a few years.
Executives in the chip industry have stated that packaging sizes will only get bigger in the future, in order to extract more computing power from chips used for AI data centers. However, there are still some technological bottlenecks, such as the difficulty in coating photoresist on the new substrate shape. The support of well-funded chipmakers like Taiwan Semiconductor is required to drive equipment manufacturers to change the design of their equipment.
Bernstein Research's semiconductor analyst, Mark Li, believes that overall, this technological change may take five to ten years to achieve comprehensive facility upgrades, including the transformation of robotic arms and automated material handling systems.
In addition to Taiwan Semiconductor, Intel and Samsung are also working with suppliers to explore panel-level packaging technology.$NVIDIA (NVDA.US)$, $Advanced Micro Devices (AMD.US)$, $Amazon (AMZN.US)$ and $Alphabet-C (GOOG.US)$As chip packaging and testing service providers such as ASE Technology, as well as display manufacturers such as BOE and Taiwan's AU Optronics, invest resources in developing panel-level chip packaging technology, innovation and diversification in the semiconductor industry are accelerating.
Taiwan Semiconductor's current advanced chip stacking and assembly technology, such as the AI chip used for data centers, mainly relies on 12-inch silicon wafers, which is the largest size currently available. However, with the increasing size of chips and the demand for more integrated memory, the current industry standard 12-inch wafer may no longer be sufficient to meet the packaging needs of cutting-edge chips within a few years.
Technology industry executives have stated that packaging sizes will only get bigger in the future, in order to extract more computing power from chips used for AI data centers. However, there are still some technological bottlenecks, such as the difficulty in coating photoresist on the new substrate shape. The support of well-funded chipmakers like Taiwan Semiconductor is required to drive equipment manufacturers to change the design of their equipment.
Bernstein Research's semiconductor analyst, Mark Li, believes that overall, this technological change may take five to ten years to achieve comprehensive facility upgrades, including the transformation of robotic arms and automated material handling systems.
In addition to Taiwan Semiconductor, Intel and Samsung are also working with suppliers to explore panel-level packaging technology.
As chip packaging and testing service providers such as ASE Technology, as well as display manufacturers such as BOE and Taiwan's AU Optronics, invest resources in developing panel-level chip packaging technology, innovation and diversification in the semiconductor industry are accelerating.
Editor/Somer