The semiconductor process has reached 3nm, trial production will begin this year, mass production will be achieved next year, and then it will be launched to 2nm and 1nm. Compared with 2nm, the current 1nm process technology is completely in the stage of research and development, and there is no landing technology and production capacity planning. It is precisely because of this that 1nm technology has more imagination and expansion space, and all walks of life of industry, university and research all over the world are carrying out research on related processes and materials.

Last week, IBM andSamsung Electronics (ADR) (SSNGY.US) $A new design for vertically stacking transistors on a chip is announced, which is called vertical transmission field effect transistor (Vertical Transport Field Effect Transistors,VTFET). In the current processor and SoC, the transistor is placed flat on the silicon surface, and the current flows from one side to the other. By contrast, VTFET are perpendicular to each other and current flows vertically. This technology is expected to break through the bottleneck of 1nm process.

IBM and Samsung say the design has two advantages. First, it can bypass many performance limitations and extend Moore's law beyond IBM's current nanoscale technology, and more importantly, the design reduces energy waste because of the higher current. They estimate that VTFET will make the processor twice as fast or 85 per cent less power than chips designed with FinFET transistors. IBM and Samsung claim that the technology is expected to allow phones to be used on a single charge for a whole week. They say it can also make some energy-intensive tasks, including encryption mining, more energy efficient and therefore have less impact on the environment.

IBM and Samsung have not disclosed when they plan to commercialize the process technology. They are not the only companies trying to break through the 1 nm bottleneck. In May this year, Taiwan Semiconductor Manufacturing Co Ltd and partners released the 1nm process technology path; in July, Intel Corp said that its goal is to complete the design of Egyptian-grade chips by 2024. The company plans to use its new "Intel Corp 20A" process nodes and RibbonFET transistors to achieve this goal.

Taiwan Semiconductor Manufacturing Co Ltd is still in the vanguard

In recent years, the scientific community has been looking for two-dimensional materials that can replace silicon to challenge the process below 1nm, but so far it has not solved the problems of high resistance and low current of two-dimensional materials.

In recent years, Taiwan Semiconductor Manufacturing Co Ltd has been a pioneer in the R & D and commercialization of advanced processes.

May this year$Taiwan Semiconductor Manufacturing Co Ltd (TSM.US) $Taiwan University of China (NTU) and Massachusetts Institute of Technology (MIT) jointly announced a major breakthrough in the research and development of 1nm chips.

This breakthrough is mainly reflected in materials. Using semi-metallic bismuth (Bi) as the contact electrode of two-dimensional (2D) materials can greatly reduce the resistance and increase the current. This can achieve energy efficiency close to the existing physical limits of semiconductor size. The news came after IBM announced its 2nm chip earlier.

Each new technology brings new challenges. In this case, the key challenge is to find the right transistor structure and material. At the same time, the transistor contacts that supply power to the transistor are crucial to its performance. The further miniaturization of semiconductor technology increases the contact resistance, which limits their performance. As a result, chipmakers need to find a contact material that has very low resistance, can transmit large currents and can be used for mass production.

Using semi-metallic bismuth as the contact electrode of the transistor can greatly reduce the resistance and increase the current. Currently, Taiwan Semiconductor Manufacturing Co Ltd uses tungsten interconnection transistors, while Intel Corp uses cobalt interconnection. Both have their advantages and require specific equipment and tools.

In order to use semi-metallic bismuth as the contact electrode of the transistor, the researchers had to use a helium ion beam (HIB) lithography system and design a "simple deposition process". This process is only used in R & D production lines, so it is not fully ready for mass production.

At present, Taiwan Semiconductor Manufacturing Co Ltd's 1nm process node is still in the exploratory stage, and the factory is trying various options, and there is no guarantee that semi-metallic bismuth will be used in future mass production.

02. IMEC points to 2027

Recently, the Belgian Microelectronics Research Center (IMEC) said that the 1nm process will be commercialized in 2027, and the subsequent 0.7nm is expected to be mass-produced after 2029.

Dr. CEO Luc Van den hove of IMEC stressed in an interview that with new technology, "it doesn't matter how many generations Moore's Law takes." It is reported that the research and development of EUV equipment jointly developed by IMEC and ASML is under way, and Japan's TEL is also involved. The test equipment is expected to be completed in early 2023, and some enterprises plan to put into mass production in 2026.

In addition, IMEC has developed a new method to reduce the Joule effect by using metal interconnects in chips constructed by 1nm process technology.

IMEC researchers say that in the experimental study of aluminum-based binary compounds, the resistivity of stoichiometric AlCu and Al2Cu films is as low as 9.5 μ Ω cm. These results support experimentally their commitment to be used as new conductors in advanced semi-mosaic interconnection integration schemes, in which they can be combined with air gaps to improve performance. However, in this combination, the Joule heat effect becomes more and more important. This is predicted by combining experimental and modeling work in a 12-tier back-end (BEOL) structure.

The 1nm process requires the introduction of new conductor materials into the most critical layers at the back end, such as binary and ternary intermetallics (e.g., Al or Ru-based), whose resistivity is lower than that of proportionally sized conventional element metals (such as Cu, Co, Mo or Ru). IMEC has studied the resistivity of aluminide films through experiments, including AlNi, Al 3 Sc, AlCu and Al 2 Cu. At the thickness of 20nm and above, the resistivity of all PVD deposited films is equal to or lower than that of Ru or Mo. The lowest resistivity of AlCu and Al 2 films of 28nm is 9.5 μ Ω cmCu-lower than that of Cu.

IMEC envisions the introduction of intermetallics into advanced semi-mosaic integration solutions, including direct etching of patterned metals to achieve higher aspect ratio lines. By gradually introducing some or all air gaps between the wires, the RC delay can be further improved. Replacing the traditional low-k dielectric with electrically isolated air gap is expected to reduce the proportional capacitance. However, the thermal conductivity of the air gap is extremely poor, which causes concern about Joule fever under operating conditions.

IMEC quantifies this challenge by performing Joule thermal "calibration" measurements at the local layer 2 metal interconnect level and modeling the results onto a 12-layer BEOL structure. The study predicts that the air gap will increase the temperature by 20%. It is found that the density of metal wires plays an important role: the display of higher metal density helps to reduce Joule heat.

"these findings are key to improving the semi-embedded metallization scheme as an interconnection option for 1nm processes," said Zsolt Tokei, an IMEC researcher and director of the nanointerconnection project. "in addition, IMEC is expanding the interconnect roadmap with other options, including hybrid metallization and new midline solutions, while addressing key challenges related to process integration and reliability."

03. How will it develop after 1nm?

When the silicon-based chip breaks through the 1nm, the quantum tunneling effect increases greatly, which will form "electron out of control" and make the chip invalid. In this case, replacing the silicon substrate of the chip may be one of the feasible ways for the further development of the chip.

Electrons can flow continuously from one gate to the next, rather than staying in the expected logic gate, which essentially makes it impossible for the transistor to be turned off.

Because the transistor consists of three terminals: source, drain and gate. The current flows from the source to the drain and is controlled by the gate, which turns the current on or off according to the applied voltage.

Both silicon and molybdenum disulfide (MoS2) have lattice structure, but the electronic effective mass passing through silicon is smaller than that of molybdenum disulfide. The silicon transistor works properly when the gate length is 5nm or longer.

The electrons of molybdenum disulfide have a higher effective mass, and their flow can be controlled by a smaller door length. Lawrence Berkeley National Laboratory has conducted experiments to verify the feasibility of this scheme, but the study is still in a very early stage.

There are more than 1 billion transistors on a 14nm process chip, and the Berkeley lab team has not yet developed a viable way to mass-produce new 1nm transistors, or even chips that use them.

But even as a proof of concept, the results here are still very important and encouraging, and it is expected that the subsequent discovery of new materials will continue to allow smaller transistor sizes and subsequently improve the energy efficiency of future chips.

China also has some bright spots

At present, the global 1nm process is in the stage of research and development, which is still several years away from commercial production. Therefore, although the commercialization level of advanced process technology in Chinese mainland area is not high, it is also following the international forefront in related theoretical research. For example, Hunan University also has an outstanding performance in the research of 1nm process technology.

In June this year, the research team of Hunan University developed an ultra-short channel vertical field effect transistor (VFET). This kind of transistor technology can make the transistor the size of 3nm, while the channel length only needs 0.65nm. In the previous process, the channel length represents the chip process, that is to say, the channel length of 0.65nm means the 0.65nm process.

That is, transistors are not arranged in parallel, they are arranged vertically. This longitudinal structure has natural short channel characteristics, the semiconductor channel is located between the bottom electrode and the top electrode, and the channel length only depends on the thickness of the material.

More importantly, the vertical field effect transistors are not arranged in parallel, but vertically. This longitudinal structure has natural short channel characteristics, the semiconductor channel is located between the bottom electrode and the top electrode, and the channel length only depends on the thickness of the material.

The researchers used vdW metal electrode integration method, using molybdenum disulfide (MoS2) as the thin layer or even monatomic layer of semiconductor channel, that is, the channel length is actually the thickness of a layer of molybdenum disulfide material, so the shortest reaches 0.65nm. Due to the different arrangement, there is no need to shorten the distance between the transistor and the transistor, just build a building block layer by layer, which makes it not entirely dependent on the high-precision lithography machine. However, the research is only the product of the laboratory, and there is still a long way to go to mass production.

05. Heading for 1nm lithography machine

The above is all about the research and development of process technology and materials, in order to achieve the landing of the 1nm process, manufacturing equipment, especially the EUV lithography machine is essential, which has to mention ASML.

At present, ASML's main shipments of EUV lithography machines are NXE:3400B and 3400C, the numerical aperture (NA) of these two models are 0.33, of which the availability of the newer 3400C has reached about 90%.

ASML expects that by the end of this year, NXE:3600D will begin to deliver, and the matching accuracy of the device has been improved. The wafer throughput under 30mJ/cm2 has reached 160, an increase of 18% compared with 3400C, and will become the main equipment of Taiwan Semiconductor Manufacturing Co Ltd and Samsung 3nm process in the future.

In addition, ASML also announced plans for the development of future third-generation lithography machines, which are NEXT, EXE:5000 and EXE:5200. Starting from EXE:5000, the numerical aperture is increased to 0.55.

0.55NA has a huge improvement over 0.33NA, including higher contrast, lower image exposure cost and so on, which is the trend of future development.

At present, the wafer, exposure clean room has approached the physical limit, now the 5nm/7nm lithography machine has become very sophisticated, equipment parts up to 100000 +, the volume of 40 containers. It is reported that the volume of the 1nm lithography machine is twice as large as that of the current 3nm.

As the lithography machine has a large number of parts and requires high-precision assembly, the whole process of lithography machine from delivery to configuration / training takes as long as two years. According to this reference calculation, the large-scale application of 0.55NA is expected to be 2025-2026, at that time, it is likely to be the trial production period of the 1nm process.

06. Conclusion

These are only the representatives of the R & D work related to the 1nm process in the industry, not all of them. It is believed that with the mass production of 3nm and the commercialization of 2nm, the research and development of 1nm process will gradually mature. it is estimated that many of these laboratory-level studies will fall to the fab, at the same time, there will be the birth of updated process and material technology.